1. Field of the Invention
The present invention relates to a data storage apparatus and a control method of the data storage apparatus.
2. Description of the Related Art
In a system which includes a memory (for example, a DRAM (Dynamic Random Access Memory)) acting as a data storage unit for storing data, a use of a memory power saving function has been conventionally adopted as a method of reducing power consumption of the system. Here, it should be noted that the power saving function of the memory is the function to transition the memory into a power saving state such as a power down state or a self refresh state.
In order to make the power saving function further effectual, Japanese Patent Application Laid-Open No. 2006-331305 discloses an interruption control unit which transitions a DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) into a power saving state and then interrupts the terminal power supply of the DDR SDRAM. Here, as a terminal circuit of the DDR SDRAM, an SSTL2 (Stub Series Terminated Logic for 2.5V) interface based on JEDEC (Joint Electron Devices Engineering Council) standards has been known.
In the terminal circuit which is compliant with SSTL2, an intermediate voltage (e.g., 1.25V) of a power supply voltage (e.g., 2.5V) of a memory system is supplied to each of plural signal line through a terminal resistor. Consequently, even if the DDR SDRAM is transitioned into the power saving state, currents can flow from the power supply for supplying the intermediate voltage to the plural signal lines, whereby power consumption according to such current flowing resultingly occurs in the terminal circuit.
Further, the transition of the DDR SDRAM into a power down mode is performed by transitioning a CKE signal of the interface into a LOW level after all memory banks of the DDR SDRAM entered an idling state. If the state is transitioned into the power saving state by changing over the signal level of only the CKE signal at the idling state, HIGH and LOW signals levels respectively exist in the interface. Therefore, if the terminal power supply is interrupted as it is, the current flows from the HIGH level signal to the LOW level signal through the terminal circuit, whereby power consumption according to the current flowing occurs.
In Japanese Patent Application Laid-Open No. 2006-331305, two interruption units for the terminal power supply are provided in order to solve such a problem as described above. That is, the HIGH level signal and the LOW level signal are controlled respectively by the independent interruption units to restrain the current from flowing when the terminal power supply is interrupted, thereby reducing the power consumption in the terminal circuit.
However, in such a method as disclosed in Japanese Patent Application Laid-Open No. 2006-331305, since the two interruption units are provided for the terminal power supply, power is still consumed in these interruption units. Thus, the power consumption increases at a time of an ordinary operation in which the memory is not transitioned into the power saving state.